The present invention relates to a multi-state Josephson memory in a superconductor integrated circuit, and in particular, to a multi-state Josephson memory with a plurality of superconducting quantum interference devices (SQUIDs).
Superconductor digital integrated circuits have shown a significant potential for high speed supercomputers, digital signal processors, high performance network switches, and analog-to-digital converters in a variety of defense and commercial applications. At the present time, a major performance limitation on high performance computing with superconductor integrated circuits is the absence of a high performance, high density superconductor memory. A conventional superconductor integrated circuit memory has a SQUID Josephson junction memory cell that stores a single flux quantum to represent a binary digit. For example, the presence or the absence of a flux quantum can be regarded as to denote a "1" or "0" signal of a binary digit, respectively. Therefore, a conventional Josephson memory can store, at most, one binary digit per SQUID.
With existing superconductor integrated circuit fabrication technology, the scale of integration of a conventional binary Josephson junction memory is very limited. An example of a high density superconductor memory known to date using Josephson junction technology is a 4-kilobit non-volatile static random access memory (SRAM). Further development to increase the scale of integration to fabricate a 16-64 kilobit memory by using sub-micron lithography with the existing superconductor processing technology significantly increases the difficulty of fabrication. Process maturity and memory cell operation margin has made the fabrication of a higher density memory with a sufficiently acceptable yield technically very challenging. The 4-kilobit non-volatile SRAM, the highest density superconductor memory known to date, is not yet fully operational due to yield limiting hard defects. Sub-micron device scaling of SQUID Josephson junction circuits would lower the yield even further as it takes more time to develop a mature process technology to provide sufficient uniformity and operational margin for a circuit layout with a large scale integration. The lack of a mature fabrication process at the present time significantly increases the production cost of a conventional high density superconductor memory with each SQUID storing only one binary digit.
Therefore, there is a need for a higher density superconductor memory that is capable of storing more information on a single memory chip for a given chip size with a scale of integration that is readily achievable by existing superconductor integrated circuit fabrication technology.